1. Technical Field
The invention relates to semiconductor device fabrication and, more particularly, to techniques for making custom connections between conductive lines (wires) of a wiring level.
2. Related Art
Modern integrated circuit (IC) chips make use of damascene wiring, from a few levels to ten or more levels. Damascene wiring is a process in which trenches and vias are formed in dielectric layers. Metal is deposited (in the trenches and vias), and excess metal is removed by means of chemical-mechanical polishing (CMP; planarization). This forms conductive lines (wires). At least two, and as many as ten or more such damascene layers (levels) may be formed. Copper (Cu) is becoming a material of choice for conductive lines (wiring, wires, conductors), due to its superior electrical characteristics. Copper exhibits about half the resistivity as compared with conventional aluminum (AlCu) wiring.
One way to take advantage of copper damascene wiring is to have a final aluminum level, which will be referred to herein as the “TM” level. (The term “TM” is not particularly meaningful, it can be thought of merely as an acronym for “top metal”. It will be, however, used as an abbreviation throughout the descriptions that follow.) In one example, aluminum (AlCu) pads are put on top of the last damascene wiring level copper pads. (The copper pads are simply enlarged areas of the copper conductive lines.) The aluminum pads protect the underlying copper pads and also provide a surface on which to do conventional C4 (Controlled Collapse Chip Connection) metallurgy. In some cases, wiring is not permitted in the aluminum (“TM”) level. Therefore, designs should be fully functional after the last copper level is completed. When the last copper wiring level is completed, the testing can be performed prior to forming the aluminum pads.
FIGS. 1A–1F illustrate an example of the copper damascene wiring with a final aluminum level, such as has been briefly described hereinabove. Only a relevant, top portion of an IC chip 100 of a semiconductor substrate (wafer) is shown—namely, a damascene interconnect structure.
Underlying damascene levels (wiring layers), underlying junctions and devices, and the underlying substrate (wafer) itself are well known and are omitted, for illustrative clarity.
As shown in FIG. 1A, a penultimate (n−1) damascene wiring layer 102 comprises a via 104 formed in (through) a dielectric (insulator) 106. The via 104 is filled (e.g., overfilled and CMP polished) with copper. In a next wiring layer 108, which is the last of the several Cu wiring levels, trenches (troughs) 110 are formed in (through) a dielectric (insulator) 112 and are filled with copper (which is then CMP polished). The last copper wiring level 108 typically has a thickness (vertical, in the figure, as viewed; perpendicular to the surface of the wafer) of approximately 1 μm (one micron) thick. (The terms “vias” and “trenches” are somewhat arbitrary when talking about damascene. They are both openings of various sizes and shapes through an insulating layer which are overfilled with conductor and then CMP planarized.)
After the last copper wiring level 108 is formed, a diffusion barrier cap 114 is deposited (atop the last copper wiring level) which is typically silicon nitride having a thickness of approximately 1000 Å (Angstroms). Next, a “LV” insulator (insulating layer) 116 is deposited (atop the diffusion barrier cap) which is typically silicon oxide having a thickness of approximately 5000 Å, followed by more silicon nitride (not shown) typically having a thickness of approximately 5000 Å. (The term “LV” is not particularly meaningful, it can be thought of merely as acronym for “Last Via”. It will however be used as an abbreviation throughout the description that follows.)
Next, as shown in FIG. 1B, photoresist (“resist”) 120 is deposited (coated) on top of the LV insulating layer 116. A LV mask 124, typically comprising a sheet of opaque material (e.g., chrome) having a plurality of openings 126 disposed therein, is located atop the LV resist 120. Then, using conventional photolithography, the resist 120 is exposed to light (arrows) through the mask openings 126, selectively altering the solubility of exposed portions of the LV resist 120 (lithographically defining openings 122 which will be made in the LV resist 120). The LV resist 120 is “positive” photoresist. “Positive” photoresist is initially insoluble, and becomes soluble as a result of radiation. (“Negative” photoresist is initially soluble, and becomes insoluble as a result of radiation.) In the developing process, the illuminated portions of the resist, which have become soluble, will be washed away, and the remaining un-illuminated portions of the resist, which remain insoluble, will act as a mask for subsequent etching, protecting the material (in this case, LV insulator) underlying these remaining portions of the resist. In other words, with positive resist you shine light on the resist where you want to etch (remove) material which is under the resist. With negative resist, you would shine light on the resist where you want to protect underlying material from being etched. The LV mask 124 is product specific—that is, it is designed to form identical features which will be present on every iteration of the product—in this case, aluminum pads (140; FIG. 1F) extending to and making a “regular” connection with selected ones of corresponding underlying copper wires, as described in further detail hereinbelow. The LV resist 120 is exposed with pad shapes corresponding to the aluminum pads (140) which will be formed.
The LV resist 120 is then developed, washing away the soluble portions (not shown) thereof, the insoluble portions remaining and defining openings 122 in the LV resist 120 over selected portions (e.g., “pad” areas, 118, better viewed in FIG. 1C) of the copper of the last copper wiring level 108. Generally, these openings 122 are relatively large in area (and low aspect ratio), typically having a width (left-to-right, as viewed; parallel to the surface of the wafer; also into the page) on the order of 10's to 100 μm. Thus, it can readily be observed that the drawing figures are “compressed”, widthwise, for illustrative clarity. If they were not compressed, they would be much wider than the page. The “pad” areas 118 of the copper of the last copper wiring level 108 are also relatively large in area as contrasted with conductive line portions of the copper which may typically only have a width of a few microns, or less.
Next, as shown in FIG. 1C, after the LV resist 120 has been developed (and the LV mask 124 has been removed), the LV insulator layer 116 and barrier cap 114 are then reactive ion etched (RIE) away (arrows) in the areas where there is no LV resist 120, so that first openings 128 are formed in (through) the LV insulator layer 116 and barrier cap 114 and extend to the selected pad areas 118 of the copper of the last copper wiring level 108. Not all the copper wires of the last copper wiring level need to have pads, only selected ones. The remaining LV resist 120 is then cleared off the LV insulator 116.
Next, as shown in FIG. 1D, after LV insulator RIE and resist clearing, aluminum metallization (“TM” level) is performed, which comprises depositing a thin barrier layer (not shown) such as 500 Å of tantalum nitride (TaN), followed by a blanket deposition of approximately one micron (1 μm) thick of TM aluminum (metal) 130. The TM aluminum 130 is conventional aluminum/copper (AlCu) comprising approximately 99.5% aluminum. The barrier layer (not shown) of titanium (Ti) or titanium nitride (TiN) or combinations can be deposited before the TM aluminum 130, for adhesion (to the underlying copper) and good contact resistance. And, if the TM aluminum 130 were intended to carry current along the wafer plane, a thin layer (not shown) of Ti/TiN could be deposited on top of the TM aluminum 130, for increased reliability. As shown in FIG. 1D, the aluminum 130 overfills the openings 128 in the LV insulator 116, and there is “excess” aluminum on the top surface of the LV insulator 116. The “excess” aluminum is generally that portion of the aluminum 130 which is not within (or immediately adjacent) an opening 128 in the LV insulator 116.
At this stage of the process, the excess TM aluminum 130 (and the adjoining metallic (e.g., TaN, TiN) layers) could be removed by CMP (chemical-mechanical polishing), in a manner similar to the underlying copper damascene levels, leaving aluminum pads in the openings 128 of the LV insulator 116, directly over and electrically connected with the copper pads 118. (This clears the top surface of the LV insulator of excess aluminum.) However, in this process, the TM aluminum 130 and the adjoining metallic (e.g., TaN, TiN) layers are patterned by conventional metal reactive ion etching (RIE), as follows.
As shown in FIG. 1E, a layer of TM resist 132 is deposited on the TM aluminum 130. The TM resist 132 is also positive resist. A TM mask 134, comprising a sheet of opaque material (e.g., chrome) having a plurality of openings 136 disposed therein, is disposed atop the resist 132. Then, using conventional photolithography, the TM resist 132 is exposed to light (arrows) through the TM mask openings 136, selectively altering the solubility of exposed portions of the TM resist 132. The TM resist 132 is then developed, washing away the soluble portions (not shown) thereof, the insoluble portions remaining. This leaves portions of TM resist 132 over the TM aluminum 130 which is over the pad portion 118 of the copper of the last copper wiring level 108.
Next, the exposed (not covered by resist) portions of the TM aluminum 130 are etched, using any suitable technique such as dry (plasma) etching, to leave aluminum pads 140 over and in electrical contact with the last wiring level copper pads 118. The edges of the TM aluminum pads 140 generally overhang the LV insulator 116, so that the edges of the aluminum pads 140 are on top of the LV insulator 116. C4 contacts or wire bonds can then be formed on the aluminum pads 140. The resulting product is shown in FIG. 1F. Subsequent layers of insulation (not shown) would be deposited, as is known. Again, it should be understood that FIGS. 1A–1F are greatly compressed (out-of-scale) in the widthwise direction. In reality, the pad 140 would be several times as wide as the page, presenting a suitably large surface area for C4 contact formation. (FIG. 1F is indeed shown with “break lines” indicating that the overall structure is wider than shown.) The process described with respect to FIGS. 1A–1F could be implemented with negative rather than positive LV resist 120 and with negative rather than positive TM resist 132.
Modern semiconductor chips can be complex mixtures of various “functions”—they can have multiple arithmetic units, data storage units, clocking units, fetching units, sequencing units, receiving and transmitting units. After all process levels are fabricated, a certain amount of testing is performed. Such tests might determine basic functionality or if certain blocks are working. Architecture decisions can be made at that point, based on yield and performance speed sort data, about whether to connect or disconnect certain functions to other designs on the chip, in order to satisfy multiple customer requests and optimize product yield. The test data can be fed forward to conventional infrared laser fuse blow tools. The present invention relates to semiconductor device fabrication and, more particularly, to techniques for making custom connections between conductive lines (wires) of a wiring level.
Back End of Line (BEOL) laser fuse blow is used to break connections. Because of insulator damage and potential for corrosion at blown fuse sites, and potential for reconnection through electromigration, each technology requires rigorous fuse qualification studies. (BEOL typically means after final metallization—more specifically, in the context of the present invention, after final wiring (copper) level has been completed and the design is fully functional.)
Front End of Line (FEOL) E-fuses are also used to break connections, but they typically leave high resistance (as opposed to essentially infinite resistance) and so are not suitable for some (e.g., high current) applications.
Poly-diffusion anti-fuses and metal-metal antifuses are used to form connections in programmable ASICs, but the resulting connections are typically of relatively high resistance, and so are also not suitable for some (e.g., high current) applications.
Laser assisted chemical vapor deposition (CVD) metal deposition or focussed ion beam techniques can be used to selectively deposit conductors and thus make custom electrical connections, but these are typically very slow processes and they require specialized vacuum equipment.
There exists a need for making and breaking connections that does not suffer from the aforementioned limitations of the prior art techniques.
Infrared (IR) light has a wavelength of 750 nm–1 mm. Visible light has a wavelength of 400–750 nm. Ultraviolet (UV) radiation has a wavelength of 100–400 nm. 1 millimeter (mm; 10−3 meters)=1000 micron (μm; 106 meters). 1 μm=1000 nanometers (nm; 10−9 meters)=10,000 Angstroms (Å; 10−10 meters)
Excimer lasers are capable of generating very shortwavelength (below 200 nm) UV radiation. For example, an ArF (argon-fluorine) excimer laser has a wavelength of 193 nm and is suitable for 150 nm (0.15 micrometer) geometry exposure, a KrF (krypton-fluorine) excimer laser has a wavelength of 248 nm and is suitable for 180 nm (0.18 (m) exposure, and a F2 (fluorine) excimer laser has a wavelength of 157 nm and is suitable for exposure of 130 nm patterns (possibly even smaller). Many excimer lasers operating in the UV range are known.